1. Field of the Invention
The present invention relates to a semiconductor storage device and its manufacturing method and, particularly, to a nonvolatile semiconductor storage device and its manufacturing method.
2. Description of Related Art
FIGS. 17-30 show a process for forming a memory cell portion of a conventional semiconductor device, particularly a nonvolatile semiconductor storage device.
As shown in FIGS. 17 and 18, device isolation regions 102 are formed on the main surface of a p-type silicon substrate 101.
As shown in FIG. 19, after the main surface of the p-type silicon substrate 101 is cleaned, a tunnel oxide film 103 of about 100 xc3x85 in thickness is formed by thermal oxidation in areas other than above the device isolation regions 102. A phosphorus-doped polysilicon film 104a of about 1,000 xc3x85 in thickness is formed on the surface of the tunnel oxide film 103 by low-pressure CVD, and then a silicon nitride film 105a of about 1,000 xc3x85 in thickness is deposited on the phosphorus-doped polysilicon film 104a. 
Then, as shown in FIG. 20, after a resist (not shown) is formed in a desired pattern on the silicon nitride film 105a by photolithography, first-layer floating gates 104b are formed by etching the phosphorus-doped polysilicon film 104a and the silicon nitride film 105a by using the resist as a mask. Silicon nitride films 105b are formed on the respective first-layer floating gates 104b. After the resist is removed, nxe2x88x92 regions (diffusion regions) 106 are formed by implanting phosphorus ions at energy of 50 eV at a dose of 2xc3x971013 cmxe2x88x922.
Then, as shown in FIG. 21, a thick silicon oxide film 107 of about 2,000 xc3x85 in thickness is deposited by low-pressure CVD.
Then, as shown in FIG. 22, sidewalls 108 of silicon oxide films are formed on the first-layer floating gates 104b by anisotropic etching. Then, annealing is performed at about 900xc2x0 C. in a nitrogen atmosphere. Then, n+ regions (diffusion regions) 109 are formed under the tunnel insulating film 103 by implanting arsenic ions at energy of 50 eV at a dose of 5xc3x971015 cmxe2x88x922.
Then, as shown in FIG. 23, a thick silicon oxide film 110 of about 4000 xc3x85 in thickness is deposited by CVD.
Then, as shown in FIG. 24, the silicon nitride films 105b on the respective first-layer floating gates 104b are exposed by etching back the silicon oxide film 110 by dry etching.
Then, as shown in FIG. 25, the silicon nitride films 105b on the respective first-layer floating gates 104b are removed by using a heated phosphoric acid.
Then, as shown in FIG. 26, the silicon oxide film 110 and the sidewalls 108 are etched back by dry etching.
Then, as shown in FIG. 27, a phosphorus-doped polysilicon film 111a of about 1,000 xc3x85 in thickness is deposited on the etched-back silicon oxide film 110 and sidewalls 108 by low-pressure CVD. Then, a resist 112 is formed in a desired pattern on the phosphorus-doped polysilicon film 111a by photolithography.
Then, as shown in FIG. 28, second-layer floating gates 111b are formed by etching the phosphorus-doped polysilicon film 111a by using the resist 112 as a mask.
Subsequently, as shown in FIG. 29, a silicon oxide film 113 of about 200 xc3x85 in thickness is deposited on the second-layer floating gates 111b and the silicon oxide film 110 by low-pressure CVD.
As shown in FIG. 30, a phosphorus-doped polysilicon film 114 is deposited on the silicon oxide film 113 and then a silicon oxide film 115 is formed on the phosphorus-doped polysilicon film 114. After a resist is patterned by photolithography, the silicon oxide film 115 and the phosphorus-doped polysilicon film 114 are patterned. The resist is then removed. Then, after a resist is formed in a peripheral circuit portion by photolithography, floating gate electrodes 111c of memory transistors are formed from the phosphorus-doped polysilicon films 111b and etched first-layer floating gates 104c are formed by etching the silicon insulating film 113, the phosphorus-doped polysilicon film 111b, and the first-layer floating gates 104b by using the silicon oxide film 115 in the memory cell portion as a mask.
Subsequently, n-channel transistors and p-channel transistors are formed in the peripheral circuit portion.
Then, a boron-phosphorus glass layer 121 of about 10,000 xc3x85 is deposited on the silicon oxide film 115 by CVD. After the boron-phosphorus glass layer 121 is burnt and tightened by performing a heat treatment at about 850xc2x0 C. for about 30 minutes in a nitrogen atmosphere, a resist (not shown) is formed in a desired pattern on the boron-phosphorus glass layer 121 by photolithography. After contact holes are formed by etching the boron-phosphorus glass layer 121 using the resist as a mask, an aluminum-silicon-copper (Alxe2x80x94Sixe2x80x94Cu) alloy film 122 is deposited by sputtering. Then, after a resist (not shown) is formed in a desired pattern by photolithography, an Alxe2x80x94Sixe2x80x94Cu wiring 122 is formed by etching the Alxe2x80x94Sixe2x80x94Cu alloy film 122 by using the resist as a mask.
In the above conventional nonvolatile semiconductor device, information (data) is stored in the memory cell transistors depending on whether electrons are injected in or released from the first-layer floating gates 104c and the second-layer floating gates 111c. In a state that electrons are injected in the first-layer floating gate 104c and the second-layer floating gate 111c, the threshold voltage of a memory cell transistor has a large value Vthp. This state is called a programmed state. In this case, data xe2x80x9c0xe2x80x9d is stored in the memory cell transistor. Since electrons accumulated in the first-layer floating gate 104c and the second-layer floating gate 111c do not disappear semi-permanently as long as they are left as they are, the stored data is also held semi-permanently.
In a state that electrons are released from the first-layer floating gate 104c and the second-layer floating gate 111c, the threshold voltage of a memory cell, transistor has a small value Vthe. This state is called an erased state. In this case, data xe2x80x9c1xe2x80x9d is stored in the memory cell transistor. Data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d that is stored in a memory cell transistor can be read out by detecting one of the programmed state and the erased state. Certain stored data may be defined as either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d; it is also possible to make a definition that data xe2x80x9c1xe2x80x9d is stored in the programmed state and data xe2x80x9c0xe2x80x9d is stored in the erased state.
In the programmed state, a high voltage Vpp (usually about 20 V) is applied to the control gate 114 and the n-type diffusion layer 109a and the silicon substrate 101 are grounded. Because of the grounding, electrons are generated in the channel that is formed between the n-type diffusion layers 109a and 109b. The electrons generated in the channel tunnel through the energy barrier of the tunnel insulating film 103 and are injected into the first-layer floating gate 104c and the second-layer floating gate 111c. As a result, the threshold voltage of the memory cell transistor increases to the large value Vthp.
At the time of erasing, a high voltage xe2x88x92Vpp (usually about xe2x88x9220 V) is applied to the control gate 114 and the n-type diffusion layer 109a and the silicon substrate 101 are grounded. Because of the grounding, electrons are released from the first-layer floating gate 104c and the second-layer floating gate 111c to the silicon substrate 101 by the tunneling phenomenon. As a result, the threshold voltage of the memory cell transistor decreases to the small value Vthe.
Each memory cell of the above conventional nonvolatile semiconductor storage device consists of a capacitor C1 that is composed of the control gate 114, the silicon oxide film 113, the second-layer floating gate 111c, and the first-layer floating gate 104c and a capacitor C2 that is composed of the second-layer floating gate 111c, the first-layer floating gate 104c, the tunnel oxide film 103, and the silicon substrate 101. The capacitances of the capaacitors C1 and C2 are represented by C11 and C22, respectively. When the voltage Vpp is applied to the control gate 114, the potential difference between the second-layer floating gate 111c/first-layer floating gate 104c and the silicon substrate 101, that is, the potential difference between both ends of the tunnel oxide film 103, increases and the electron tunneling probability increases as the capacitance C11 becomes larger. The increased electron tunneling probability increases the write/erase speed.
The capacitance C11 is in proportion to the surface area of the second-layer floating gate 111c. In the conventional nonvolatile semiconductor storage device, the surface area of the second-layer floating gate 111c is restricted by the memory cell size. This causes a problem that as the memory cells are miniaturized, the capacitance C11 decreases and the write/erase speed of the memory cell transistors lowers.
To solve the problem that the write/erase speed of the memory cell transistors lowers, another conventional nonvolatile semiconductor storage device (e.g., one disclosed in Japanese Patent Laid-Open No. 7-106442) employs the following measure. That is, to increase the write/erase speed of the memory cell transistors, the surface area of the second-layer floating gate 111c is increased by forming irregularity, that is, many minute spherical crystals, on the surface of the second-layer floating gate 111c. 
However, the above conventional measure that is taken to increase the write/erase speed of the memory cell transistors results in a problem that electric fields are concentrated on the protrusions on the surface of the second-layer floating gate 111c and the reliability of the silicon oxide film 113 that is the insulating film located between the control gate 114 and the second-layer floating gate 111c is thereby lowered, whereby the storage device is rendered not suitable for practical use.
The present invention has been made to solve the above problems in the art, and an object of the invention is therefore to provide a semiconductor device and its manufacturing method which not only can solve the problem that the memory cell size determines the write/erase speed of the memory cell transistors but also can increase the write/erase speed while preventing the reduction in the reliability of the insulating film between the control gate 114 and the second-layer floating gate 111c. 
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a first conductivity type; device isolation regions formed on a main surface of the semiconductor substrate; a tunnel insulating film formed on the main surface of the semiconductor substrate except for the device isolation regions; a first-layer floating gate formed on the tunnel insulating film; diffusion regions having a second conductivity type formed at both ends of the first-layer floating gate; an insulating film having irregularity formed over the diffusion regions having the second conductivity type and the device isolation regions; a second-layer floating gate having irregularity formed on the insulating film; and a control gate formed on the second-layer floating gate, wherein the insulating film formed under the second-layer floating gate and on the first-layer floating gate and the insulating film formed on the device isolation regions, respectively, have raised portions.
According to a second aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising the steps of: forming device isolation regions on a main surface of a semiconductor substrate having a first conductivity type; forming a tunnel insulating film on the main surface of the semiconductor substrate except for the device isolation regions; forming a first-layer floating gate on the tunnel insulating film; forming diffusion regions having a second conductivity type at both ends of the first-layer floating gate; forming an insulating film having irregularity over the diffusion regions and the device isolation regions; forming a second-layer floating gate having irregularity on the insulating film; and forming a control gate on the second-layer floating gate, wherein the insulating film located under the second-layer floating gate and on the diffusion regions having a second conductivity type and the insulating film on the device isolation regions, respectively, are formed to be convex.
According to a third aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a first conductivity type; device isolation regions formed on a main surface of the semiconductor substrate; a tunnel insulating film formed on the main surface of the semiconductor substrate except for the device isolation regions; a first-layer floating gate formed on the tunnel insulating film; diffusion regions having a second conductivity type formed at both ends of the first-layer floating gate; an insulating film formed over the diffusion regions having a second conductivity type and the device isolation regions; island-like Si3N4 portions formed on the insulating film; a second-layer floating gate having a roughened shape and formed on the Si3N4 portions; and a control gate formed on the second-layer floating gate.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.